首页> 外文会议>2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip. >An efficient method to localize and correct bugs in high-level designs using counterexamples and potential dependence
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An efficient method to localize and correct bugs in high-level designs using counterexamples and potential dependence

机译:使用反例和潜在的依赖关系来定位和纠正高级设计中的错误的有效方法

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摘要

As high-level design draws more attention and has been adopted more widely, verification and debugging for high-level designs has become more important. In this paper, we propose a method to find possible corrections for given counter-examples, targeting high-level design descriptions. To efficiently find corrections, program slicing technique and constraints generated from counterexamples are applied to reduce the number of initial bug candidates and debugging scope. Through the experiments, we show that the proposed method with the reduction efficiently works for several example designs and bugs, and successfully identifies bug locations.
机译:随着高层设计越来越引起人们的注意并被更广泛地采用,高层设计的验证和调试变得越来越重要。在本文中,我们提出了一种针对高级设计说明针对给定反例找到可能的更正的方法。为了有效地找到更正,应用了程序切片技术和从反例生成的约束,以减少初始错误候选的数量和调试范围。通过实验,我们表明所提出的具有减少量的方法可以有效地用于几个示例设计和错误,并且可以成功地识别错误位置。

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