The purpose of this paper is to demonstrate the successful design of passive high power multi-stage limiters operating from 33 to 36 GHz using a high-yielding GaAs Vertical PIN diode process. Measured CW data shows that a two stage design achieves less than 0.5 dB insertion loss while achieving a flat leakage of about 21 dBm. A three stage design achieves 0.8 dB small signal insertion loss and 19 dBm flat leakage. A key to achieving the performance was the accurate large signal modeling of the PIN diodes.
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