Numerical simulation of polysilicon TFTs based on discrete grain boundaries

摘要

Numerical simulations of grain boundaries barriers and drain current are carried out in polysilicon thin-film transistors based on discrete grain boundaries (GBs). The height of grain boundary barrier was analyzed under various biases conditions and drain induced grain barrier lowering (DIGBL) effect was observed. The influence of trap states density in GBs on current characteristics was also studied and simulated. The transfer characteristics with various drain-to-source voltages are demonstrated.