A 23.1#x00B5;W 8 Bit 1.1 MS/s SAR ADC with counter based control logic

摘要

This paper presents the implementation of Successive Approximation Architecture (SAR) based Analog to Digital Convertors (ADC). In order to reduce the power consumption and increase the speed, a double-tail latch type comparator is incorporated in the design. Charge redistribution DAC is used for area efficiency. A synchronous type SAR Logic with counter based controlled unit is proposed for faster operation. The structure is designed and simulated using 0.18 µm CMOS technology. The ADC consumes 23.1 µW power achieving a figure of merit of 119 fJ/conv-step and ENOB of 7.46.