Design and verification of integrated inductors in CMOS

摘要

The design and verification of several monolithic inductor structures is presented. Based on the measurement results of proof-of-concept prototypes in 65 nm CMOS, the inductance (L) and quality factor (Q) of these structures are analyzed both qualitatively and quantitatively. Also, a closed-form approximation for the inductance of vertical spirals is presented and the results are applied to design a compact inductor for serie-speaking at the input of an impedance-matched amplifier.