首页> 外文会议>2011 38th Annual International Symposium on Computer Architecture >Crafting a usable microkernel, processor, and I/O system with strict and provable information flow security
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Crafting a usable microkernel, processor, and I/O system with strict and provable information flow security

机译:制作具有严格且可证明的信息流安全性的可用微内核,处理器和I / O系统

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High assurance systems used in avionics, medical implants, and cryptographic devices often rely on a small trusted base of hardware and software to manage the rest of the system. Crafting the core of such a system in a way that achieves flexibility, security, and performance requires a careful balancing act. Simple static primitives with hard partitions of space and time are easier to analyze formally, but strict approaches to the problem at the hardware level have been extremely restrictive, failing to allow even the simplest of dynamic behaviors to be expressed. Our approach to this problem is to construct a minimal but configurable architectural skeleton. This skeleton couples a critical slice of the low level hardware implementation with a microkernel in a way that allows information flow properties of the entire construction to be statically verified all the way down to its gate-level implementation. This strict structure is then made usable by a runtime system that delivers more traditional services (e.g. communication interfaces and long-living contexts) in a way that is decoupled from the information flow properties of the skeleton. To test the viability of this approach we design, test, and statically verify the information-flow security of a hardware/software system complete with support for unbounded operation, inter-process communication, pipelined operation, and I/O with traditional devices. The resulting system is provably sound even when adversaries are allowed to execute arbitrary code on the machine, yet is flexible enough to allow caching, pipelining, and other common case optimizations.
机译:航空电子设备,医疗植入物和加密设备中使用的高保证系统通常依赖于小型的受信任的硬件和软件基础来管理系统的其余部分。以实现灵活性,安全性和性能的方式来设计这种系统的核心需要谨慎的平衡。具有空间和时间硬分区的简单静态基元更易于形式化分析,但是在硬件级别对问题的严格方法却极为严格,甚至无法表达最简单的动态行为。我们解决此问题的方法是构造一个最小但可配置的架构框架。该框架将低级硬件实现的关键部分与微内核耦合在一起,从而可以静态验证整个结构的信息流属性,直至其门级实现。然后通过运行时系统使这种严格的结构可用,该运行时系统以与框架的信息流属性分离的方式提供更多传统服务(例如,通信接口和长期使用的上下文)。为了测试这种方法的可行性,我们设计,测试和静态验证了硬件/软件系统的信息流安全性,并支持无边界操作,进程间通信,流水线操作以及与传统设备的I / O。即使允许对手在计算机上执行任意代码,最终的系统也可以证明是可靠的,但它具有足够的灵活性以允许缓存,流水线和其他常见情况优化。

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