Step-ami-Flash Imprint Lithography (S-FIL™) Enabling 32nm Patterning for Unit Process Development

摘要

The traditional "Grand Challenge" in the ITRS Roadmap has been the ability to improve the performance of MOSFETs by aggressively scaling gate lengths in high performance applications. This was limited by the capabilities of lithography and with the successful implementation of immersion lithography, MOSFET scaling is no longer expected to be "lithography-limited," rather the current situation is now described in the ITRS FEP roadmap as "material-limited device scaling." Therefore, in order to advance device scaling in logic devices, materials and process technologies need to be investigated at fine geometries to identify and overcome fundamental technical barriers. This requires high resolution patterned test wafers to develop and qualify materials and processes for 32nm and beyond.