A Novel CMOS Down-conversion Mixer with Current Reuse Technique

摘要

A novel low voltage and power mixer topology for SGHz wireless LAN applications is presented in this paper. To reduce power dissipation, a novel mixer topology with a low supply voltage and using the current reuse technique is designed using a 0.18 蘭 CMOS process. The designed down-conversion mixer has a conversion gain of 7.5dB, a P1dB of -16Bm and an IIP3 of -6dBm, respectively, with LO power of -7dBm while consuming 1.6mA under a 1.5V supply voltage. The chip size including pads is 0.77mm x 0.81mm.