A Built-in Test Scheme for Pipelined Multipliers and Dividers

摘要

An embedded test patterm generator scheme in large-operand multiplier and divider is presented by applying simple digital circuit. This scheme is based on the generation of cyclic code polynomials from a characterized polynomials generator G(X). Only full adders / subtractors and shift registers are used in the proposed multiplier and divider hardware. The input data of the multiplier/divder can be processed in parallel or in pipelined without considering carry/borrow delays during the operations. The speed of computation has therefore been greatly improved by approximately a factor of 2. Since most parts of the components can be both used in the multiplier and divider, just one full adder is applied in the multiplier to be replaced by a subtractor in the divider. The structure is therefore tremendously reduced. In addition, this hardware can be incorporated with a cyclic code generator t perform built-in self-test (BEST).