BEOL TODAY AND TOMORROW: CAN WE TURN ITRS'S 'NO KNOWN SOLUTIONS' TO 'NOVEL NANO SOLUTIONS' ?

摘要

After the introduction of Cu as wiring metal in manufacturing, the implementation of intermetal dielectrics with values of the dielectric constant below that of SiO_2, so called low-k materials, will be the next big challenge in the BEOL to reduce RC, the signal delay determined by the product of line resistance and line capacitance. Both the properties of these materials and their integration in the BEOL complicate the selection of the proper material from a large number of candidates. Further planar scaling requires the knowledge of the scaling limits for the functionality of both the conductor and the barrier layers. Cu will stay the conductor of choice in the future. Estimations show that device delay rather than local interconnect delay will be the performance limiter even if size effects will be taken into account. Whenever the end of planar scaling will become reality, when excessive hierarchical wiring and even when novel architectures will not lead to further increase in system and chip performance, nano technology with carbon nanotube based elements may allow further progress in microelectronics. It will go on!