Electro-thermal high-level modeling of integrated circuits

摘要

Operating temperature and temperature gradients are of critical concern in the design of planar integrated circuits (ICs) and are bound to be exacerbated in the upcoming 3D technologies. However, a thermal aware design of ICs allows thermal issues to be kept to the minimum. Previously, a simulator integrated in the Cadence^® environment that allows electro-thermal simulations to be carried out at transistor levels has been presented. In this paper, a methodology used to build high-level electro-thermal model compliant with this simulator is detailed.