Debugging VHDL Designs Using Temporal Process Instances

摘要

In this paper we outline the usage of model-based diagnosis for fault localization in VHDL-RTL designs. In contrast to previous research, our approach makes use of temporal aspects of a VHDL program. The facts that the conversion of the VHDL program to a logical representation can be done automatically, and that a standard model-based diagnosis engine can be used, make the approach easy to implement and use. In the first part of the paper, we show how a model can be used to compute diagnosis for a VHDL program. In the second part, we introduce a new logical model that allows the diagnosis engine to deal with temporal information directly by unfolding the circuit with respect to time, thereby employing temporal instances of VHDL processes.