FPGA Implementation of Novel Routing Algorithm for Butterfly-Fat-Tree Topology based NoC Design

摘要

This paper presents a novel routing algorithm for Butterfly-Fat-Tree (BFT) topology based Network-on-Chip (NoC) design. It proposes a routing algorithm along with router addressing scheme for BFT topology which can be used in any generic NoC router architecture. The proposed algorithm has been implemented in software using C, followed by hardware implementation using Verilog. It has been validated using FPGA based hardware and the results show that proposed routing algorithm routes the data from source to destination seamlessly. This can be incorporated with NoC router architecture to verify several functionalities on a hardware based prototype.