Design and Realization of a Low Power Register File Using Energy Model

摘要

This paper uses a analytical-based characterization model to discuss energy consumption of register files with different circuit techniques that using multi-port SRAM technology. Energy distribution chart of register file with different architectural parameters is acquired according to the calculation results of energy model. How the decoder structure and the dominant component have effect on the power of the register file is demonstrated with emphasise. With this low power method, a 64x32 bits three-port register file operate at a 500MHz frequency with 54mW power dissipation.