In this paper a technique to reduce the leakage power in the register file is presented. Power gating is one of the commonly used technique to reduce the subthreshold leakage current. But as the technology scales down, the effect of the leakage current increases since the supply voltage and the threshold voltage also has to be scaled down with technology scaling. With the power gating technique applied to the register file, it introduces a continuous leakage from the data retention element used to store the data. Since, it has to be powered up always to hold the data present in the register file. Thus an alternative technique called the supply switching with ground collapse technique (SSGC) is implemented where the supply is switched from the normally applied supply voltage to the lower voltage under the standby condition to reduce the leakage current compared to power gating technique. In this paper both of the above mentioned techniques is applied to the register file array of 8x8 with multiple read and write ports and leakage analysis is carried out in a Vdd=1V, 45nm CMOS technology. Also in this paper, the voltage and temperature variation is done to show the power variations.
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