Fault Detection for Testable Realizations of Multiple-valued Logic Functions

摘要

The testable realization techniques of logic functions can be used for circuit design to reduce the complexity of test pattern generation. The circuit testable realizations of multiple-valued logic functions are investigated in this paper. The multiplication modulo gates and addition modulo gates are used in the testable realization. It is shown that n+2 test vectors are sufficient to detect the Min and Max bridging faults in the testable realizations, where n is the number of input variables of multiple-valued functions. The delay in circuit can be decreased if the tree structure is employed instead of cascade structure. It is indicated that for the tree structure realizations with m-valued logic, the number of single fault test vectors is three if m-2 extra inputs and an addition modulo gate are added. Furthermore, the multiple faults detection approach of the circuit realizations is investigated, a multiple faults test set is given.