Conflict-Avoidance-Driven Test Generation and Test Point Insertion for Transition Faults in Broadside Scan Testing

摘要

Test pattern generation of a transition fault for a broadside scan designed circuit is partitioned into two time frames based on the single stuck-at fault test generation. Test generation of a transition fault in a broadside scanned circuit is to drive the signal requirements in the second frame away from the pseudo-primary inputs that can be influenced by the specified inputs in the first frame. Potential conflicts produced by the signal requirements on the pseudo-primary outputs must also be avoided. The signal requirements at the pseudo-primary inputs of the second frame are partitioned into separate connected components based on an input dependency graph. Test pattern generation reduces to satisfaction of the signal related to the signal requirements connected components one by one. Control test points are inserted away from the testable critical paths to satisfy the necessary signal requirements of the faults that are testable for enhanced scan testing, but are untestable in the broadside scan testing. New techniques are used to reduce the pin overhead based on the two time-frame circuit model.Sufficient experimental results are resented to demonstrate the efficiency of the proposed method.