A GRAPHICS PROCESSING ARCHITECTURE EMPLOYING A UNIFIED SHADER

摘要

A graphics processor, comprising an arbiter circuit having vertex data provided at a first input and pixel data provided at a second input, wherein arbiter circuit is configured to select to transmit the vertex data at the first input or the pixel data at the second input; and a unified shader coupled to the arbiter circuit, wherein the unified shader is configured to simultaneously perform the vertex operations and the pixel operations on the vertex data and the pixel data by switching between the vertex operations and the pixel operations, and the unified shader comprises: a register block coupled to the arbiter circuit configured to maintain the vertex data and the pixel data in the unified shader, a processor unit coupled to the register block, wherein the processor unit is configured to execute vertex operations and pixel operations, and a sequencer coupled to the processor unit and the register block, wherein the sequencer is operative to cause the processor unit to execute the vertex operations and the pixel operations on the vertex data and the pixel data.