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Instruction Set Architecture and Microarchitecture for Early Pipeline Re-steering Using Load Address Prediction to Mitigate Branch Misprediction Penalties
Instruction Set Architecture and Microarchitecture for Early Pipeline Re-steering Using Load Address Prediction to Mitigate Branch Misprediction Penalties
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机译:用于早期管道重新引导的指令集体系结构和微体系结构使用负载地址预测来减轻分支预测失误的惩罚
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摘要
Methods and apparatus relating to Instruction Set Architecture (ISA) and/or microarchitecture for early pipeline re-steering using load address prediction to mitigate branch misprediction penalties are described. In an embodiment, decode circuitry decodes a load instruction and Load Address Predictor (LAP) circuitry issues a load prefetch request to memory for data for a load operation of the load instruction. Compute circuitry executes an outcome for a branch operation of the load instruction based on the data from the load prefetch request. And re-steering circuitry transmits a signal to cause flushing of data associated with the load instruction in response to a mismatch between the outcome for the branch operation and a stored prediction value for the branch. Other embodiments are also disclosed and claimed.
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