ANALOG IN-MEMORY COMPUTING BASED INFERENCE ACCELERATOR

摘要

A compute cell (10) for in-memory multiplication of a digital data input (X) and a balanced ternary weight (w) is disclosed and an in-memory computing device comprising an array thereof. The compute cell comprises a set of input connectors (11a, 11b) for receiving modulated input signals (A+, A-) representative of a sign and a magnitude of the digital data input, and a memory unit (12) configured for storing the balanced ternary weight. A logic unit (13) of the compute cell is connected to the set of input connector and the memory unit (12) to receive the data input and the balanced ternary weight, and is adapted to selectively enable one of a plurality of conductive paths for supplying a partial charge to a read bit line (S; S+, S-) during a compound duty cycle (T) of the set of input signals as a function of the respective signs of data input and ternary weight, and to disable each of the plurality of conductive paths if at least one of the balanced ternary weight and data input have zero magnitude. The compound duty cycle is indicative of the data input magnitude.