According to the present invention, an operation unit for outputting an error correction message by performing an iterative decoding operation on a first codeword; a syndrome generator generating a syndrome by calculating the error correction message and a parity check matrix, and outputting a number of iterations of the iterative decoding operation and an unsatisfied check node (UCN) value included in the syndrome; and a speed selector for outputting a speed code for adjusting the speed of the iterative decoding operation according to the number of repetitions and the UCN value, wherein the calculating unit resets the speed of the iterative decoding operation according to the speed code, An error correction decoder that performs the iterative decoding operation according to a reset speed when two codewords are input, an error correction circuit including the same, and an operating method of the error correction decoder.
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