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System, apparatus and method for symbolic store address generation for data-parallel processor
System, apparatus and method for symbolic store address generation for data-parallel processor
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机译:用于数据并行处理器的符号存储地址生成的系统,装置和方法
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摘要
In one embodiment, an apparatus includes: a plurality of execution lanes to perform parallel execution of instructions; and a unified symbolic store address buffer coupled to the plurality of execution lanes, the unified symbolic store address buffer comprising a plurality of entries each to store a symbolic store address for a store instruction to be executed by at least some of the plurality of execution lanes. Other embodiments are described and claimed.
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