Computation of neural network node by neural network inference circuit

摘要

Some embodiments provide a neural network inference circuit (NNIC) for executing a neural network that includes multiple computation nodes, that include dot products, at multiple layers. The NNIC includes multiple dot product core circuits and a bus, including one or more aggregation circuits, that connects the core circuits. Each core circuit includes (i) a set of memories for storing multiple input values and multiple weight values and (ii) a set of adder tree circuits for computing dot products of sets of input values and sets of weight values stored in the set of memories. For a particular computation node, at least two of the core circuits compute partial dot products using input values and weight values stored in the memories of the respective core circuits and at least one of the aggregation circuits of the bus combines the partial dot products to compute the dot product for the computation node.