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Energy efficient processor core architecture for image processor
Energy efficient processor core architecture for image processor
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机译:用于图像处理器的节能处理器核心架构
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摘要
An apparatus that includes a program controller to fetch and issue instructions is described. The apparatus includes an execution lane having at least one execution unit to execute the instructions. The execution lane is part of an execution lane array that is coupled to a two dimensional shift register array structure, wherein, execution lane s of the execution lane array are located at respective array locations and are coupled to dedicated registers at same respective array locations in the two-dimensional shift register array.
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