Systems and methods for implementing configurable convolutional neural networks with flash memory

摘要

A memory array is provided having memory cells arranged in rows and columns. Each memory cell includes a source region and a drain region with a channel region interposed therebetween, a floating gate disposed over the first channel region portion, and a second gate disposed over the second channel region portion. Each of the plurality of bit lines extends along one of the columns and is electrically connected to drain regions of one or more memory cells of a first group of memory cells in the column, and is electrically connected to the drain regions of one or more of the memory cells in the column. electrically isolated from the drain regions of the one or more memory cells of the second group. Each of the plurality of source lines is electrically connected to source regions of memory cells in one of the columns or rows. Each of the plurality of gate lines is electrically connected to second gates of memory cells in one of the columns or rows.