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Controlling clocks and resets in a logic built in self-test
Controlling clocks and resets in a logic built in self-test
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机译:控制在自检中构建的逻辑中的时钟和重置
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摘要
A method for testing a design is provided. The method includes generating a sequence of bits, mapping the sequence of bits to a combination, and generating an enable signal based on the combination. The enable signal enables an asynchronous signal in the design. The method also includes driving an element of the design based on the enabled asynchronous signal.
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