FIELD PLATE AND ISOLATION STRUCTURE FOR HIGH SPANISH BUILDINGS

摘要

An integrated chip has a field plate that is above an isolation structure. A gate electrode is located over a substrate between a source area and a drain area. An etching stopper layer extends laterally from a surface of the gate electrode to a front of the substrate. The etching stop layer is located over a drift area that is located between the source area and the drain area. The field plate is arranged within a first intermediate layer of dielectric (ILD) layer,which lies above the substrate. The field plate extends from a surface of the ILD layer to a surface of the etching stopper layer. The isolation structure is arranged within the substrate and extends from the front of the substrate to a point below the front of the substrate. The isolation structure is positioned laterally between the gate electrode and the drain area.