BIT SHUFFLE PROCESSORS METHODS SYSTEMS AND INSTRUCTIONS

摘要

The processor includes packed data registers and a decode unit for decoding instructions. The instruction indicates a first source operand having at least one bit lane and a second packed source data operand having a plurality of sublane size bit select elements. The execution unit is coupled with the packed data register and the decode unit. The execution unit, in response to the instruction, stores the result operand in the destination storage location. The result operand includes a different corresponding bit for each of the plurality of sublane size bit selection elements. The value of each bit of the result operand corresponding to the sublane size bit selection element is the value of the bit of the corresponding bit lane, which is at least one bit lane of the first source operand, indicated by the corresponding sublane size bit selection element. am.