首页>
外国专利>
BIT SHUFFLE PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS
BIT SHUFFLE PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS
展开▼
机译:BIT SHUFFLE处理器,方法,系统和说明
展开▼
页面导航
摘要
著录项
相似文献
摘要
A processor includes packed data registers and a decode unit to decode an instruction. The instruction is to indicate a first source operand having at least one lane of bits, and a second source packed data operand having a number of sub-lane sized bit selection elements. An execution unit is coupled with the packed data registers and the decode unit. The execution unit, in response to the instruction, stores a result operand in a destination storage location. The result operand includes, a different corresponding bit for each of the number of sub-lane sized bit selection elements. A value of each bit of the result operand corresponding to a sub-lane sized bit selection element is that of a bit of a corresponding lane of bits, of the at least one lane of bits of the first source operand, which is indicated by the corresponding sub-lane sized bit selection element.
展开▼