MOS arrangement with diode-based gate coupling for improved ESD properties and layout technology for this

摘要

A semiconductor arrangement comprising: a semiconductor body (140) of a first conductivity type; a doped drain region (102) of a second conductivity type, which is arranged on a surface of the semiconductor body (140), the second conductivity type being opposite to the first conductivity type; a doped source region (108) of the second conductivity type, which is arranged on the surface of the semiconductor body (140) and is laterally spaced from the doped drain region (102) by a region of the first conductivity type; a gate (104), of which at least a partial region is insulating over the region of the first conductivity type, the gate (104) having a first region (146) of the second conductivity type adjacent to the doped source region (108) and the doped drain region (102), whereby a second diode region is formed, and a second region (144) of the first conductivity type directly connected to the first region (146) of the second conductivity type adjacent, thereby forming a first diode region; and a signal pad (110) arranged on the semiconductor body (140), the signal pad (110) being coupled to the doped drain region (102), wherein a diode (141) connected between the gate (104) and the source region (108); 147) is formed by the first diode region (144) and the second diode region (146), an interface between the first and second diode regions forming a first semiconductor junction, and the first diode region (144) being connected to the doped source region (108) and the second diode region (146) is coupled to the gate (104), and wherein the gate (104) further comprises a silicided region (142) which is arranged over a portion of the second region (144) of the first conductivity type, wherein the silicided region ( 142) does not extend over the first semiconductor junction.