首页> 外国专利> Memory bank power coordination including concurrently performing a memory operation in a selected number of memory regions

Memory bank power coordination including concurrently performing a memory operation in a selected number of memory regions

机译:内存银行电源协调包括在所选数量的内存区域中同时执行内存操作

摘要

Apparatuses and methods related to memory bank power coordination in a memory device are disclosed. A method for memory bank power coordination may include concurrently performing a memory operation by a threshold number of memory regions, such as banks or subarrays, and executing a command to cause a budget area, such as a register, to perform a power budget operation associated with the memory operation. The threshold number of memory regions may be set based at least in part on a threshold power consumption value, and the number of memory regions to concurrently perform an operation may be controlled by a bank arbiter. A counter having a value representing the threshold number of memory regions may be decremented while performing an operation or incremented upon completion of an operation associated with one of the memory regions. A number of the memory regions may be selected to perform a processing-in-memory operation.
机译:公开了与存储器设备中的存储器组电力协调相关的装置和方法。 用于存储器组电源协调的方法可以包括通过阈值数量的存储区(例如银行或子阵列)同时执行存储器操作,以及执行命令以使诸如寄存器的预算区域,以执行相关联的电力预算操作 通过内存操作。 可以至少部分地基于阈值功耗值来基于阈值功耗值来设置阈值数量,并且可以由银行仲裁器控制以同时执行操作的存储区域的数量。 具有表示阈值数量的存储区数的计数器可以在执行操作时递减,或者在完成与其中一个存储区域相关联的操作时递增。 可以选择许多存储区域以执行处理内存操作操作。

著录项

  • 公开/公告号US11107510B2

    专利类型

  • 公开/公告日2021-08-31

    原文格式PDF

  • 申请/专利权人 MICRON TECHNOLOGY INC.;

    申请/专利号US201916657445

  • 申请日2019-10-18

  • 分类号G11C8/12;G11C7/10;G11C11/4076;G11C11/4074;G06F12/06;G11C11/408;G11C11/4096;G06F13/16;

  • 国家 US

  • 入库时间 2022-08-24 20:50:51

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