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INTEGRATED CIRCUIT WITH SELF-TEST CIRCUIT, METHOD FOR OPERATING AN INTEGRATED CIRCUIT WITH SELF-TEST CIRCUIT, MULTI-CORE PROCESSOR DEVICE AND METHOD FOR OPERATING A MULTI-CORE PROCESSOR DEVICE
INTEGRATED CIRCUIT WITH SELF-TEST CIRCUIT, METHOD FOR OPERATING AN INTEGRATED CIRCUIT WITH SELF-TEST CIRCUIT, MULTI-CORE PROCESSOR DEVICE AND METHOD FOR OPERATING A MULTI-CORE PROCESSOR DEVICE
An integrated circuit with self-test circuit is provided. The integrated circuit includes at least one logic circuit, at least one input storage element for storing work data, at least one output storage element, an input test storage element for storing test data, and at least one output test storage element, wherein the logic circuit is selectively connected to the input storage element on the input side, such that the input storage element provides the work data to the logic circuit, or is connected to the input test storage element on the input side, such that the input test storage element provides the test data to the logic circuit, wherein the logic circuit is further connected to the output storage element and the output test storage element on the output side, such that the logic circuit feeds data to the output storage element and/or to the output test storage element, and wherein the output storage element is configured to process the data from the logic circuit if the work data are provided to the logic circuit, and not to process the data from the logic circuit if the test data are provided to the logic circuit.
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