Hardware Complexity Reduction Techniques for Continuous Elimination List Decoders

摘要

The present invention discloses a hardware complexity reduction method for successive cancellation list decoders (SCL). In the path pruning step of SCL decoding, the L paths with the smallest path metrics among the 2L candidate paths are selected as surviving candidate paths as in the existing SCL algorithm. In addition, the path indices of the L surviving candidate paths are provided in an ordered manner according to the indices in the output of the sorter module. After path pruning, an L(L/2+1)-to-1 multiplexer is deployed instead of an L-to-1 multiplexer to perform copy operations of all essential elements stored in the path's dedicated registers.