Elmore Delay Time (EDT) Based Resistance Model

摘要

An integrated circuit design tool for modeling the resistance of terminals of transistors such as gates, sources, drains and vias is disclosed. The structure of the terminal is specified in the data structure of the memory using a three-dimensional (3D) coordinate system. For each of the plurality of volume elements in the designated structure, an Elmore delay time (EDT) is determined. For this volume element among the plurality of volume elements located on the surface of the gate terminal facing the channel region, an average EDT (aEDT) is determined based on the EDT. The terminal's point-to-point resistance values are generated as a function of aEDT and the terminal's capacitance.