A compute-in-memory bitcell is provided that includes a pair of cross- coupled inverters for storing a stored bit. The compute-in-memory bitcell includes a logic gate for multiplying the stored bit with an input vector bit. The logic gate comprises a FET transistor. The source terminal of the FET transistor is connected to the output node of the cross-coupled inverters, the gate terminal of the FET transistor is connected to the input vector bit and the drain terminal of the FET transistor is connected to a first plate of a capacitor. The second plate of the capacitor is connected to a read bit line.
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