FULLY DIGITAL VOLTAGE MONITOR (ADVM) WITH SINGLE CYCLE LATENCY

摘要

A fully digital voltage monitor (ADVM) generates a multi-bit output code that changes in proportion to a voltage that is being monitored by taking advantage of the voltage's effect on a gate delay. ADVM uses a simple delay chain that receives a clock cycle-long pulse every clock cycle, so that the monitored supply voltage is sampled for a full cycle every cycle. The outputs of all delay cells of the delay chain together represent a current voltage state as a digital thermometer code. In AVDM, a voltage drop event thus leads to a decrease in the output code from a nominal value, while an overshoot leads to an increase in the output code.