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SILICON STRUCTURE WITH DIELECTRIC INSULATION FOR HIGH-VOLTAGE MICROSCIRCUITS IN SMALL CASES

机译:硅结构具有介电绝缘的小案例中的高压微观曲线

摘要

The proposed utility model relates to the design of silicon structures with dielectric insulation for high-voltage microcircuits, namely, for microcircuits in small-sized packages with a supply voltage of more than 200 V.;The technical result of the proposed utility model is to increase the breakdown voltage without increasing the forward voltage drop and crystal thickness.;The specified technical result is achieved by the fact that a silicon structure with dielectric insulation for high-voltage microcircuits, consisting of a silicon-based substrate, isolated by a dielectric from the substrate of silicon monocrystalline pockets with two hidden layers, the first doped with arsenic, and emerging on the working surface of the structure along the side walls of the pockets, the second, at the bottom of the pocket, doped with phosphorus with a dose in the range (2.5-3.5) ⋅10 13 ions / cm 3 and a depth greater than the depth of arsenic by 4-6 microns and a high-voltage planar junction on the working side of a silicon structure with dielectric insulation, consisting from the flat part, along the periphery of which there are elements increasing the breakdown voltage of the planar junction, while the second hidden layer is formed only under the flat part of the planar junction.
机译:所提出的本实用新型涉及一种用于高压微电路的介电绝缘硅结构的设计,即小型封装中的微电路,电源电压大于200 V.;所提出的实用新型的技术结果是增加击穿电压而不增加正向电压降和晶体厚度。;指定的技术结果是通过具有用于高压微电路的介电绝缘的硅结构,由硅基衬底组成,由电介质隔离具有两个隐藏层的硅单晶袋的基板,第一层掺杂砷,并在袋侧壁的结构的工作表面上,第二,在口袋底部,掺杂有剂量的磷在范围(2.5-3.5)⋅10 13 离子/ cm 3 ,深度大于砷的深度4-6微米和高压p Lanar结在硅结构的工作侧具有介电绝缘,由平坦部分组成,沿着周边,有元件增加平面结的击穿电压,而第二隐藏层仅在平坦的部分下形成平面交界处。

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