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AVOIDING DEADLOCKS IN PROCESSOR-BASED SYSTEMS EMPLOYING RETRY AND IN-ORDER-RESPONSE NON-RETRY BUS COHERENCY PROTOCOLS
AVOIDING DEADLOCKS IN PROCESSOR-BASED SYSTEMS EMPLOYING RETRY AND IN-ORDER-RESPONSE NON-RETRY BUS COHERENCY PROTOCOLS
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机译:避免在基于处理器的系统中的死锁,采用重试和响应响应的非重试总线一致性协议
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摘要
Aspects disclosed herein include avoiding deadlocks in processor-based systems employing retry and in-order-response non-retry bus coherency protocols. In this regard, an interface bridge circuit is communicatively coupled to a first core device that implements a retry bus coherency protocol, and a second core device that implements an in-order-response non-retry bus coherency protocol. The interface bridge circuit receives a snoop command from the first core device, and forwards the snoop command to the second core device. While the snoop command is pending, the interface bridge circuit detects a potential deadlock condition between the first core device and the second core device. In response to detecting the potential deadlock condition, the interface bridge circuit is configured to send a retry response to the first core device. This enables the first core device to continue processing, thereby eliminating the potential deadlock condition.
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