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Mitigation of cache-latency based side-channel attacks

机译:基于缓存延迟的侧通道攻击缓解

摘要

Particular embodiments described herein provide for an electronic device that can be configured to receive a request for data, wherein the request is received on a system that regularly stores data in a cache and provide the requested data without causing the data or an address of the data to be cached or for changes to the cache to occur. In an example, the requested data is already in a level 1 cache, level 2 cache, or last level cache and the cache does not change its state. Also, a snoop request can be broadcasted to acquire the requested data and the snoop request is a read request and not a request for ownership of the data. In addition, changes to a translation lookaside buffer when the data was obtained using a linear to physical address translation is prevented.
机译:这里描述的特定实施例提供了可以被配置为接收对数据的请求的电子设备,其中在经常存储高速缓存中的数据的系统上接收到请求,并在不引起数据的情况下提供所请求的数据或数据的地址要缓存或更改缓存。在一个示例中,所请求的数据已经在1级缓存,级别2缓存或最后级别缓存中,并且缓存不会改变其状态。此外,可以广播窥探请求以获取所请求的数据,并且Snoop请求是读取请求,而不是对数据的所有权的请求。另外,在使用线性地获取数据到物理地址转换时,对翻译后保护缓冲器的改变。

著录项

  • 公开/公告号US11055226B2

    专利类型

  • 公开/公告日2021-07-06

    原文格式PDF

  • 申请/专利权人 INTEL CORPORATION;

    申请/专利号US201816022782

  • 发明设计人 VADIM SUKHOMLINOV;

    申请日2018-06-29

  • 分类号G06F12;G06F12/08;G06F13;G06F12/0875;G06F12/1027;G06F21/55;G06F12/0897;

  • 国家 US

  • 入库时间 2022-08-24 19:44:08

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