Device and methods for reducing peak noise and peak power consumption in semiconductor devices under test

摘要

A test device includes a test mounting circuit having a plurality of semiconductor devices mounted thereon as respective devices-under-test. Each device-under-test includes a corresponding delay control circuit and a target circuit therein. Test logic is provided, which is electrically coupled to the test mounting circuit. The test logic is configured to generate a test input(s), which is provided in parallel to the delay control circuits within the plurality of devices-under-test. The delay control circuits include at least first and second delay control circuits, which are configured to pass the test input(s) to corresponding first and second target circuits during respective first and second test time intervals that are out-of-phase relative to each other in order to achieve more uniform power consumption requirements of the test mounting circuit during testing.