SAMPLING CLOCK PHASE MISMATCH ERROR ESTIMATION METHOD AND APPARATUS, AND STORAGE MEDIUM

摘要

A sampling clock phase mismatch error estimation method and apparatus, and a storage medium. The sampling clock phase mismatch error estimation method comprises: obtaining the proportional relation between an estimation operator of a modular subtraction method corresponding to each of a plurality of frequency ranges and a TIADC sampling clock phase mismatch error; calculating the slope and offset value of a fitted proportional segment between an actual sampling clock phase mismatch error value and an estimated sampling clock phase mismatch error value corresponding to a frequency demarcation point of each frequency range; and in real-time estimation of the TIADC sampling clock phase mismatch error, converting the estimated sampling clock phase mismatch error value obtained according to the estimation operator of the modular subtraction method into the slope of the proportional segment corresponding to a real-time estimated frequency, estimating the offset value corresponding to the real-time estimated frequency by means of interpolation according to the calculated slope and offset value, and estimating an actual error value of sampling clock phase mismatch on the basis of the slope obtained by conversion and the offset value estimated by means of interpolation.