SHARED SOURCE LINE STORAGE ARCHITECTURE FOR BYTE-CHANGEABLE FLASH CELL DATA STORAGE WITH LONG SERVICE LIFE

摘要

A memory array includes (a) a plurality of memory cells arranged in a plurality of bytes, (b) a separate word line connected to each byte, and (b) a plurality of shared source lines, each are connected to at least two bytes so that each byte in the array can be addressed by a separate word line and by the shared source line. Because of this memory array architecture, a program operation on a first byte applies a common source line voltage to an unselected second byte (with a reverse voltage applied to bit lines connected to the second byte), creating a corresponding fault condition, the corresponds to a diagonal (or line) programming failure condition in a conventional memory array. The use of the shared source lines can reduce the number of source line drivers required, thereby reducing the overhead area of the memory array while allowing backward compatibility with conventional byte-wise variable EEPROM.