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Method and apparatus for supporting automatic testbench parallelism and serial equivalence checking during verification
Method and apparatus for supporting automatic testbench parallelism and serial equivalence checking during verification
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机译:用于支持自动测试牢的并行性和串行等效检查在验证期间的方法和装置
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摘要
A method for designing a system on a target device includes performing high-level compilation on a high-level language source file to generate a hardware description language (HDL) of the system and a serial testbench for the system. Verification is performed on the system that examines a parallel nature of the system by using the serial testbench.
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