High speed NAND memory system and high speed NAND memory package device

摘要

A switching buffer that controls switching so that a plurality of NAND memory chips constituting the NAND memory package device transmits a plurality of page-unit data in parallel through the NAND interface is provided between the NAND memory chip and the host controller. The performance of the NAND memory system can be improved by increasing the data transmission/reception speed between host controllers.