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Method, system, and product for generating and maintaining a physical design for an electronic circuit having sync group constraints for design rule checking

机译:用于生成和维护具有同步组约束的电子电路的物理设计的方法,系统和产品,用于设计规则检查

摘要

An approach is described for a method, system, and product, the approaching includes identification of an integrated circuit design, identification of sync groups (nets having synchronous voltage levels), generation of a physical design having sync group constraints, and performance of design rule checking on a physical design based on at least transferred sync group information. This provides for performing design rule analysis at least using small minimum spacing requirements then would otherwise be required with prior techniques. In some embodiments, the approach includes a verification process that ensures that synchronous voltage behavior is appropriately associated with members of respective sync groups and cleans up old association data that is no longer relevant/correct.
机译:方法,系统和产品描述了一种方法,该方法包括识别集成电路设计,识别同步组(具有同步电压电平的网),生成具有同步组约束的物理设计,以及设计规则的性能基于至少传输的SYNC组信息检查物理设计。这提供了至少使用小的最小间距要求执行设计规则分析,否则将需要使用现有技术。在一些实施例中,该方法包括验证过程,其确保同步电压行为与各个同步组的成员适当地相关联,并清除不再相关/正确的旧关联数据。

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