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SCALABLE RUNTIME VALIDATION FOR ON-DEVICE DESIGN RULE CHECKS
SCALABLE RUNTIME VALIDATION FOR ON-DEVICE DESIGN RULE CHECKS
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机译:可扩展的运行时验证用于设备上的设计规则检查
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摘要
An apparatus to facilitate scalable runtime validation for on-device design rule checks is disclosed. The apparatus includes a memory to store a contention set, one or more multiplexors, and a validator communicably coupled to the memory. In one implementation, the validator is to: receive design rule information for the one or more multiplexers, the design rule information referencing the contention set; analyze, using the design rule information, a user bitstream against the contention set at a programming time of the apparatus, the user bitstream for programming the one or more multiplexors; and provide an error indication responsive to identifying a match between the user bitstream and the contention set.
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