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Cache coherent node controller for scale-up shared memory systems having interconnect switch between a group of CPUS and FPGA node controller
Cache coherent node controller for scale-up shared memory systems having interconnect switch between a group of CPUS and FPGA node controller
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机译:缓存相干节点控制器,用于比例共享内存系统,其中一组CPU和FPGA节点控制器之间具有互连开关
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摘要
The present invention relates to cache coherent node controllers for scale-up shared memory systems. In particular it is disclosed a computer system at least comprising a first group of CPU modules connected to at least one first FPGA Node Controller configured to execute transactions directly or through a first interconnect switch to at least one second FPGA Node Controller connected to a second group of CPU modules running a single instance of an operating system.
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