Improvements in devices for the internal organisation and co-ordination of the transfer of information in an electric computing machine

摘要

932,291. Programming arrangements for computers. COMPAGNIE DES MACHINES BULL. June 20, 1960 [June 24, 1959], No. 21587/60. Class 106 (1). Transfer of data (and instructions) in a digital computer between a main store and peripheral and processing units is effected by use of address stores containing addresses in the main store associated with the units (these addresses being modifiable) one such address store being provided for data to be transferred, and a second for instructions for the unit. Fig. 2 shows at 1 the main store with input and output buffers 2 and 3, and address selector 13 receiving from data address store 15 the main store address appropriate to the particular peripheral unit 10 (only one is shown) operative for a data transfer. The connection of a unit 10 to register 7 is controlled by " priority " circuits as described in Specification 883,655, and the register 7 obtains from 15 at its " peripheral unit address " the address in store 1; this is modified (e.g. by addition of one) at 20 before being written back into 15. If a data transfer from 10 is called for, 7 will receive, in addition, the " catena " of 24 bits for transfer via 14 and 2 to main store; in the case of a transfer to 10, this takes place via register 8. The transfer of instructions (e.g. from main store to arithmetic unit or to a peripheral unit) is effected by similar means (Fig. 3, not shown) a separate address store for instructions in the main store being provided, and a register receives all instructions for " preparatory decoding " enabling the instruction to be correctly routed, ensuring that any jump modifications, address modifications (e.g. where " relative addressing " is used) are first effected, and that necessary initial conditions are satisfied. Specification 891,935 also is referred to.