Apparatus for testing binary-coded decimal arithmetic digits by binary parity checking circuits

摘要

The invention relates to parity checking in arithmetic circuits utilizing binary-coded decimal operands, and provides, inter alia, means to calculate a parity bit for the output of an arithmetic circuit from the inputs to the circuit. In Fig. 2A, two binary-coded operands A1- A4, B1- B4 with associated parity bits PA, PB are stored in registers 26, 27. Assuming that these operands are binary-coded decimal digits of numbers supplied serially by decimal digit which are to be added, control line t is energized (ONE bit) and decimal modifier 21 adds six to operand B1-B4 to produce modified operand BE1-BE4 which is added to operand A1-A4 in binary adder 20 producing result S1-S4. If a carry bit ONE is also produced by adder 20 on line 212, result S1-S4 is passed through decimal corrector 22 unchanged to constitute final result R1-R4 but otherwise six is subtracted from it in corrector 22. On the other hand, if the operands are to be subtracted, decimal modifier 21 simply inverts each bit B1-B4, achieved by energizing control line c which also constitutes an input C IN to adder 20 to add in an extra one to convert the ones complement form of operand B1-B4 supplied to the adder to twos complement form. Decimal corrector 22 operates as before. As a further mode of operation, if the operands A1-A4 and B1-B4 are to be treated as pure binary, energization of control line b ensures that decimal modifier 21 and decimal corrector 22 pass their inputs unchanged. As the above calculations are performed, the circuit of Fig. SB is adjusting parity bits correspondingly and performing a parity check. Parity modifier 23 receives operand bits B2, B3 and parity bit PB and produces a parity bit PBE corresponding to the output BE1-BE4 from decimal modifier 21. Binary parity predictor/checker 24 checks the parity of operand A1-A4 against parity bit PA and that of BE1-BE4 against PBE and produces an output at 17 in the absence of error. It also (from bits A1-A4, BE1-BE4 and control bit c alone and using ripple-carry addition) produces a parity bit PS to correspond to the output S1-S4 of adder 20. A parity corrector 25 produces a final parity bit PR to correspond to final result R1-R4, corrector 25 being fed with bit PS and result bits S2-S4. Both parity modifier 23 and parity corrector 25 also receive control bits t, c, b. The following possible forms for adder 20 are mentioned: ripple carry, carry propagate, carry lookahead, carry save, and carry eliminate. Modifications mentioned.-Binary adder 20 may be replaced by a subtracter. Adder 20 may deal with several decimal characters in parallel. Operation may be entirely serial. The excess-six code may be replaced by excess-three.