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A circuit arrangement for producing signals of predetermined amplitude and duration,in dependence on pulse code modulated signals

机译:根据脉冲编码调制信号产生预定幅度和持续时间的信号的电路装置

摘要

1,028,430. Transistor pulse shaping circuits. TELEFONAKTIEBOLAGET L. M. ERICSSON. March 21, 1963 [March 21, 1962], No. 11349/63. Heading H3T. [Also in Division G4] In a circuit for regenerating pulse code modulated signals, e.g. in a decoder, the seven-digit binary signal P1, Fig. 1 (not shown), is converted into parallel form in a tapped delay line FL whose respective outputs are connected via gates G1 to G7, controlled by timing pulses P2, P3, to electronic switches S1 to S7. The electronic switches provide pulses of constant amplitude and duration which are added in a resistance network RN in known manner to provide an analogue output. Fig. 2 shows details of the output of a portion K1, K2 of the delay lines FL. In the absence of pulses P1, P2, the diodes D1, D2 in the gate G1 are conducting so that point A is at zero potential and transistor T1, in a regenerative amplifier forming electronic switch S1 is blocked. When pulses P1, P2 occur simultaneously, the diodes D1, D2 are blocked, the 6 volts potential at point A causes transistor T1 to conduct and the regenerative feedback causes the potential at point A to fall and diode D3 to conduct. This causes an increase in the base current of transistor T1 and consequently an increase in the collector current providing an output signal at point C. To ensure that all output pulses have the same duration an inhibiting circuit H including a transistor T2 is controlled by pulses P3. In the absence of pulses P3 the transistor T2 and diode D4 are blocked and have no effect on the circuit S1. When a pulse P3 is fed to the base of the transistor T2 it will conduct and the resulting fall of potential at the collector will cause D4 to conduct and block transistor T1, the output pulses in all the circuits S1, S2 &c. ceasing simultaneously. A diode D5 in the collector circuit of transistor T1 eliminates the voltage peak which would arise due to the interruption of the current through the winding of transformer TR.
机译:1,028,430。晶体管脉冲整形电路。 TELEFONAKTIEBOLAGET L.M.ERICSSON。 1963年3月21日[1962年3月21日],编号11349/63。标题H3T。 [也在G4分部中]在用于再生脉冲编码调制信号的电路中,例如在解码器中,图1的七位二进制信号P1(未显示)在抽头延迟线FL中转换为并行形式,其延迟时间分别由门G1至G7连接,并由定时脉冲P2,P3控制,电子开关S1至S7。电子开关提供具有恒定幅度和持续时间的脉冲,以已知方式将其添加到电阻网络RN中以提供模拟输出。图2示出了延迟线FL的部分K1,K2的输出的细节。在没有脉冲P1,P2的情况下,门G1中的二极管D1,D2导通,使得点A处于零电位,并且在形成电子开关S1的再生放大器中,晶体管T1被阻挡。当脉冲P1,P2同时出现时,二极管D1,D2处于阻塞状态,A点的6伏电势使晶体管T1导通,而再生反馈使A点的电势下降而二极管D3导通。这导致晶体管T1的基极电流增加,因此导致在点C处提供输出信号的集电极电流增加。为了确保所有输出脉冲具有相同的持续时间,由脉冲P3控制包括晶体管T2的禁止电路H 。在没有脉冲P3的情况下,晶体管T2和二极管D4被阻塞并且对电路S1没有影响。当将脉冲P3馈送到晶体管T2的基极时,它将导通,并且集电极处的电势下降将导致D4导通并阻塞晶体管T1,所有电路S1,S2和c中的输出脉冲。同时停止。晶体管T1的集电极电路中的二极管D5消除了由于通过变压器TR的绕组的电流中断而产生的电压峰值。

著录项

  • 公开/公告号GB1028430A

    专利类型

  • 公开/公告日1966-05-04

    原文格式PDF

  • 申请/专利权人 TELEFONAKTIEBOLAGET L M ERICSSON;

    申请/专利号GB19630011349

  • 发明设计人

    申请日1963-03-21

  • 分类号H03K5/15;H03M1/00;

  • 国家 GB

  • 入库时间 2022-08-23 14:44:23

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